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FRoSt Lab
Field Robotic Systems Lab

Efficient Hardware Implementations or Robotics Algorithms via HLS

Improving the efficiency of robotics perception, estimation, and planning algorithms through the use of High-Level Synthesis (HLS) to generate custom FPGA circuitry.

What is High-Level Synthesis?

High-Level Synthesis (HLS) is a hardware design method that uses high-level abstraction to optimize and implement RTL on an FPGA. It allows designers to create custom digital circuits by using languages such as C, C++ or OpenCL.

Why High-Level Synthesis?

Using hardware description languages like Verilog or VHDL to design the hardware is usually complicated and time-consuming. HLS provides an easier way to implement the same algorithm by merely using a high-level language. It simplifies and speeds up the design process.

Our Goal

While HLS is a very useful tool, optimizing its results still requires expert knowledge of the FPGA and hardware design. Our goal is to create an open-source tool that enables hardware acceleration of robotic algorithms with minimal required user hardware knowledge.